Image of a lamella of the metal stack from a
recent technology node (12 copper layers)With
the transistor layer at the bottom. The TEM
lamella sample shows the construction analysis of
the device. The dark regions are the copper
layers, Thicker layers at the top are for
carrying mainly power signals. The bright regions
in between the copper layers are Low k based
dielectrics to help with capacitance issues
and increase speed performance of the chip.
Image of one transistor showing the gate oxide
region. Various other layers and process step
regions can also be observed which are involved
in the transistor construction.
High magnification TEM image of the Gate oxide region within the selected transistor. The measurement shows a
gate oxide thickness of 63 Angstroms. The 3 distinct regions of the transistor can be observed. The poly Silicon
layer to the top of the image, the gate oxide region itself, in the middle and the bulk silicon region to the
bottom which is based on wafers from Silicon  plane direction.
Energy filtered TEM images showing an elemental map of the various elements used in the construction of the transistor and device stack. False colour is used to help distinguish each element.
This technique is useful for construction analysis and also for failure analysis, i.e.Looking for defects and/or contamination between layers and process steps.